Abstract—A novel ultra high speed, compact and least sensitive to process variation, hybrid sense amplifier is designed for ultra low power SRAM. Precisely sized current mode circuit (CMC) is designed to provide differential current from bit-lines. We eliminate the global sensing stage to save silicon area and sized the output buffers to achieve full logic swing at the output of proposed sense amplifier. The proposed design improves the sensing delay and shows excellent tolerance to process variations as compared to best published latch type sense amplifier. Extensive post layout simulation results based on 45nm standard CMOS technology have verified that 38.8% reduction in sensing delay and 83.6% reduction in power dissipation is achieved compared to the best published designs under similar cell current (Icell) and bitline capacitances. The total power delay product is 0.22fJ. Furthermore, the new design can operate down to a supply voltage of 0.6V. These attribute of the proposed sense amplifier makes it judiciously appropriate for the use in the contemporary wireless sensor SRAM macro, which continuously pine for ultra low power and high-speed characteristics. In addition, the proposed design exhibits low sensitivity to bitline and dataline capacitance, capacitance mismatch. 

Index Terms—SRAM, read/write static noise margin, CMC, power, speed, sense amplifier, CMC.

Cite: B.S. Reniwal and S. K. Vishvakarma, "A Reliable, Process-Sensitive-Tolerant Hybrid Sense Amplifier for Ultralow Power SRAM," International Journal of Electronics and Electrical Engineering, , Vol. 1, No. 1, pp. 34-38, March 2013. doi: 10.12720/ijeee.1.1.34-38