A 6.5-μV/°C Offset Drift Compensation Technique for Dynamic Comparator
Daiki Tabira and Kenichi Ohhata
Department of Electrical and Electronics Engineering, Kagoshima University, Kagoshima, Japan
Abstract—The offset drift of a dynamic comparator was analyzed using a simple model in order to clarify the offset drift mechanism. We found that it was possible to nullify the offset drift component due to size variability by controlling the gate common voltage (Vcom). We conducted experiments to validate our estimations by using a test chip fabricated in 180-nm CMOS technology. Consequently, we found that the amount of variability of VTH and W/L could be extracted from the measured offset voltage. Moreover, the offset drift was reduced to 6.5 μV/°C by controlling the temperature dependence of Vcom.
Index Terms—offset drift, comparator, analog-to-digital converter, CMOS analog circuits
Cite:Daiki Tabira and Kenichi Ohhata, "A 6.5-μV/°C Offset Drift Compensation Technique for Dynamic Comparator," International Journal of Electronics and Electrical Engineering, Vol. 1, No. 1, pp. 44-47, March 2013. doi: 10.12720/ijeee.1.1.44-47
Index Terms—offset drift, comparator, analog-to-digital converter, CMOS analog circuits
Cite:Daiki Tabira and Kenichi Ohhata, "A 6.5-μV/°C Offset Drift Compensation Technique for Dynamic Comparator," International Journal of Electronics and Electrical Engineering, Vol. 1, No. 1, pp. 44-47, March 2013. doi: 10.12720/ijeee.1.1.44-47
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