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Development of Verification Environment for AXI Bus Using SystemVerilog

Xu Chen, Zheng Xie, and Xin-An Wang
Key Lab of Integrated Micro-Systems Science Engineering and Applications, Peking University Shenzhen Graduate School, Shenzhen, China
Abstract—System-on-a-Chip (SoC) design has become more and more complexly. How to verify a design effectively has become a serious challenge. In this paper, how to build up the effective verification environment of AXI using SystemVerilog is introduced. Firstly, the design under verify (DUV) AXI bus is introduced. Then a comprehensive analysis of the verification plan has been made according to the protocol. The proposed integrated verification environment with Functional coverage, score-boarding, assertions and constrained random vectors generation is implemented. With this environment, a high coverage and less time spending verification has been achieved. 
 
Index Terms—SystemVerilog, SoC, AXI, Verification Environment

Cite: Xu Chen, Zheng Xie, and Xin-An Wang, "Development of Verification Environment for AXI Bus Using SystemVerilog," International Journal of Electronics and Electrical Engineering, Vol. 1, No. 2, pp. 112-114, June 2013. doi: 10.12720/ijeee.1.2.112-114
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