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A System-Level SOC Verification Method based on Hardware Accelerator

Shi-Jun Li, Zheng Xie, and Xin-An Wang
The Key Lab of Integrated Microsystems, Peking University Shenzhen Graduate School, Shenzhen, China
Abstract—A system-level SOC verification method based on hardware accelerator is proposed in this paper. The storage mapping relationship is designed according to storage characteristics of the hardware accelerator, and the whole testbench is put into the accelerator directly, resulting in a quick migration to accelerator and an optimized memory area. In order to ensure the comprehensiveness, complexity and authenticity, the system feature description is extracted from different application scenarios, and the test cases are derived from the paths of data flow and control flow. Additionally, the system debugging is simplified by controlling the acceleration processing with the method of trigger-driver-based state transition diagram. By adopting the system-level verification method proposed in this paper, RTL design of a DSP chip is verified and the experiment results demonstrate an immense acceleration effect and a high accuracy in bug locating. Finally the DSP chip is implemented in 0.18um CMOS process and it works properly. 

Index Terms—system-level SOC verification, hardware accelerator, storage mapping, trigger

Cite: Shi-Jun Li, Zheng Xie, and Xin-An Wang, "A System-Level SOC Verification Method based on Hardware Accelerator," International Journal of Electronics and Electrical Engineering, Vol.1, No.3, pp.135-139, September 2013. doi: 10.12720/ijeee.1.3.135-139
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