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Performance and Evaluation Sobel Edge Detection on Various Methodologies

Hong Nguyen.T.K.1, 2, Cecile. Belleudy 1, and Tuan.V.Pham 2
1. Laboratory of Electronic, Antenna Telecomunication, University of Nice Sophia Antipolis, Nice, France
2. Electronic & Telecommunication Engineering Dept, Danang University of Technology, Danang, VietNam
Abstract—This paper compares various methodologies for the design of Sobel Edge Detection Algorithm on Field Programmable Gate Arrays (FPGAs). We show some characteristics to design a computer vision algorithm to suitable hardware platforms. We evaluate hardware resources and power consumption of Sobel Edge Detection on two studies: Xilinx system generator (XSG) and Vivado_HLS tools which both are very useful tools for developing computer vision algorithms. The comparison the hardware resources and power consumption among FPGA platforms (Zynq-7000 AP SoC, Spartan 3A DSP) are analyzed. The hardware resources by using Vivado_HLS on both platforms are used less 9 times with BRAM_18K, 7 times with DSP48E, 2 times with FFs, and approximately with LUTs comparing with XSG. In addition, the power consumption on Zynq-7000 AP SoC spends more 30% by using Vivado_HLS than by using XSG tool and for Spartan 3A DSP consumes a half of power comparing with by using XSG tool. In the study by using Vivado_HLS shows that power consumption depends on frequency.

Index Terms—Sobel Edge Detection, Xilinx System Generator, Vivado_HLS, hardware resources, power consumption

Cite: Hong Nguyen.T.K., Cecile. Belleudy, and Tuan.V.Phams, "Performance and Evaluation Sobel Edge Detection on Various Methodologies," International Journal of Electronics and Electrical Engineering, Vol. 2, No. 1, pp. 15-20, March 2014. doi: 10.12720/ijeee.2.1.15-20
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