Abstract—This paper presents a novel design of switch capacitor DAC successive approximation analog to digital converter (SAR-ADC) using regulated clocked current mirrors. The regulated clocked current mirror (RCCM) design is introduced to source (and sink) the constant current to (and from) the only capacitor in the circuit. The RCCM functions dynamically providing invariable current when required. Moreover when active, RCCM is capable of stabilizing the output current even in presence of voltage variations at its output. DC reference current from RCCM, charging or discharging the single capacitor in the circuit, is controlled by pulse width modulated signal to realize switch-capacitor DAC. Verilog-A script is written for switch control scheme to generate the control signals for RCCM. A dynamic latched comparator is employed to reduce the power consumption in circuit. An 8-bit SAR ADC that exhibits a maximum sampling frequency of 100 kHz is designed in 90 nm CMOS technology and its working is verified through circuit level simulations. This ADC achieves signal to noise and distortion ratio (SNDR) of 45.62 dB which corresponds to effective number of bits (ENOB) of 7.3 bits. At 1 V supply and 100 kS/s, power consumption in ADC is 6 μW while the calculated peak values of DNL and INL are +1.06/-0.40 LSB and +0.53/-1.33 LSB respectively.

Index Terms—SAR ADC, switch-capacitor DAC, regulated clocked current mirrors, Verilog-A, dynamic comparator

Cite: Ashish Joshi, Satinder Sharma, Sanjeev Manhas, and S. Dasgupta, "A Switch-Capacitor DAC Successive Approximation ADC Using Regulated Clocked Current Mirror," International Journal of Electronics and Electrical Engineering, Vol. 2, No. 1, pp. 50-55, March 2014. doi: 10.12720/ijeee.2.1.50-55