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A Fast Locking Digitally Controlled PLL for Constant-Gain Digitally Controlled Oscillator

Chen Xin and Zhang Wanqiao
College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, Jiangsu, 210016, China
Abstract—A fast locking digitally controlled phase-locked loop (DCPLL) with a novel frequency search algorithm is presented in this paper. The proposed frequency search algorithm can predict the target code by two predetermined codes and the two corresponding digital phase errors. To implement the proposed frequency algorithm in the PLL, a DCPLL with a constant-gain digitally controlled oscillator is developed and implemented in SMIC 0.13µm 1P8M technology. Finally, the frequency acquisitions are simulated for the whole frequency range. The simulation results show that the maximum locking time of the DCPLL is four reference clock cycles.

Index Terms—digitally controlled phase-locked loop (DCPLL), fast locking, digitally controlled oscillator (DCO)

Cite: Chen Xin and Zhang Wanqiao, "A Fast Locking Digitally Controlled PLL for Constant-Gain Digitally Controlled Oscillator," International Journal of Electronics and Electrical Engineering, Vol. 2, No. 2, pp. 95-100, June 2014. doi: 10.12720/ijeee.2.2.95-100
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