Abstract—A phase locked loop circuit that uses Phase Frequency Detector with NOR gates and divide-by-64 with pseudo-NMOS divide-by-2 frequency divider is proposed, designed and simulated in TSMC 0.18um 1P6M CMOS process technology to come up with minimum chip area and achieve fast lock-in time. This PLL design is specifically intended for Continuous-Time Sigma-Delta ADC operating at 640MHz frequency which is an important component of ICs used in electronics and communication devices whose clock rates and timing relationships are vital. This work has a lock-time of around 2.5us which is a fast lock-in value for the lock-in time of ADC clock generator. The desired output frequency which is 640 MHz is achieved on all corners ranging from 608 MHz to 672 MHz which is within 640MHz ±5% tolerance. In terms of the charge pump current, the proposed design used 77uA which is within the typical values of charge pump current ranging from 10uA to 100u. The PLL displays minimum total chip core area which is 8.3393 nm2 and 0.2049 um2 for off-chip and on-chip filter, respectively.

Index Terms—phase locked loop, frequency synthesizer, sigma-delta ADC, phase detector, pseudo-NMOS dividers, charge pump

Cite: Jefferson A. Hora, Christina A. Garcia, Stella Sofia I. Sabate and Meriam Gay Bautista, "Fast Lock-in Time Phase Locked Loop Frequency Synthesizer for Continuous-Time Sigma-Delta ADC," International Journal of Electronics and Electrical Engineering, Vol. 2, No. 4, pp. 259-263, December 2014. doi: 10.12720/ijeee.2.4.259-263