Abstract—This paper presents the Verilog HDL implementation of a Universal Synchronous/ Asynchronous Receiver/Transmitter (USART). The proposed design exhibits enhance power efficiency compared to the standard USART 8251a, which dissipates 48.2462 μW. To make the USART more power efficient, the basic block and pins for mode and control instructions had been modified so that the individual blocks were only activated when each had a certain function to execute. The standard function of a USART is implemented in the researcher’s design, being able to do Serial-to-Parallel and Parallel-to-Serial data conversion and have both synchronous and asynchronous modes. The total chip area is 2046.05682μm2.

Index Terms—asynchronous communication, data transmission, parallel communication, peripheral, RS 232, serial communication, synchronous communication, verilog HDL

Cite: Jefferson Hora, Meriam Gay Bautista, Kramer C. Chua, and Demie Mae V. Dajao, "Verilog HDL Implementation of a Universal Synchronous Asynchronous Receiver Transmitter," International Journal of Electronics and Electrical Engineering, Vol. 2, No. 4, pp. 264-269, December 2014. doi: 10.12720/ijeee.2.4.264-269