Abstract—A sigma-delta third order dual truncation MASH 2-1 D/A converter with 18-bit input format is successfully implemented in 90nm CMOS technology. This design focuses on the digital implementation of 64x upsampling digital interpolator and third-order delta-sigma MASH architecture. The interpolator is digitally designed by two cascading halfband FIR lowpass filter and the final stage is designed using CIC (Cascaded Integrator-Comb) filter. The third-order delta-sigma MASH modulator is implemented into two parts; these are digital part and analog part. The digital part is successfully implemented using RTL code while the analog part is thru MATLAB for behavioral and Cdesigner for actual implementation. The total area for the digital block is 30339.259853 μm2 while the total cell area is 25918.75 μm2 using the TSMC 0.13μm Logic CMOS Technology. Furthermore, the total dynamic power of the circuit (modulator and interpolator) while in operation is 11.1799 μW. With the 3rd-order dual truncation multistage noise shaping technology, SFDR of 110dB and SNR of 115 dB is achieved and its measured harmonics are all below -100dB. The total harmonic distortion of the whole analog block which has a chip area of 681um by 365um is 173m% and with a total power dissipation of 688.279uW.

Index Terms—digital-to-analog converter, 1-bit DAC, 8-bit DAC, dual-truncation, analog lowpass filter, butterworth lowpass filter

Cite: Olga Joy Labajo-Gerasta, Mycel Capilayan, Mark Laurence Dandan, and Sittie Aleyah Magayo-ong, "3rd–Order Dual Truncation 18-Bit Audio MASH 2-1 Delta-Sigma Digital to Analog Converter in 90nm CMOS Technology Implementation," International Journal of Electronics and Electrical Engineering, Vol. 2, No. 4, pp. 276-280, December 2014. doi: 10.12720/ijeee.2.4.276-280