Abstract—A study[1] shows that the data came from operational tests of systems between 1985 to 1990 and 1996 to 2000, the percentage of systems meeting reliability requirements decreased from 41 percent to 20 percent.As system complexity increases, testability is alarming in almost every applications development.There is a need to put more efforts to address the issues of testability at the device, board and system level in order to deliver more consistently reliable and cost effective products to the market. In the current industry, the highest acceptable defects parts per millions,DPM is 500 DPM or lower. To achieve 200 DPM in matured process that typically yield 99%, the test coverage requirement is 98%. This paper will address the DC coverage improvement through the proposed gate strength aware modeling.

Index Terms—ATPG modeling,ASIC, DC coverage

Cite: Boon Chong Ang and Eng Lian Goh, "Gate Strength Aware DC Coverage Improvement," International Journal of Electronics and Electrical Engineering, Vol. 2, No. 4, pp. 281-285, December 2014. doi: 10.12720/ijeee.2.4.281-285