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3-D Solenoid Inductor Analysis in a 0.13 μm Digital CMOS Technology

Chul Nam 1, Byeungleul Lee 2, Hyeon Cheol Kim 3, Jinseok Kim 4, Dong Wook Chang 5, and Bonghwan Kim 6
1. R&D Center/Siliconharmony, Seong Nam-Si, Korea
2. Mechatronics Engineering, Korea University of Technology and Education, Chungnam, Korea
3. Electrical Engineering, University of Ulsan, Ulsan, Korea
4. Center for Bionics, Biomedical Research Institute, Korea Institute of Science and Technology, Seoul, Korea
5. Chemical Systematic Engineering, Catholic University of Daegu, Gyeongbuk, Korea
6. Electronics Engineering, Catholic University of Daegu, Gyeongbuk, Korea
Abstract—This paper presents the analysis of a small-area on-chip solenoid inductor using the 0.13μm digital CMOS process. The on-chip solenoid inductor is vertically constructed using metal and via layers with a horizontal scalability. This gives the advantage of occupying a small area due to its 3-D structure compared to a spiral inductor. The electrical characteristics of the solenoid inductor have been analyzed by employing 3-D EM simulation. The proposed equivalent model of the solenoid inductor is introduced to get the insight of the scalability so that the selection of the inductance is simply choosing the number of turns. This small area solenoid inductor can be good candidate for LC type VCO for GHz PLL in the standard CMOS process with saving die cost.

Index Terms—solenoid inductor, Voltage Controlled Oscillator, EM simulation

Cite: Chul Nam, Byeungleul Lee, Hyeon Cheol Kim, Jinseok Kim, Dong Wook Chang, and Bonghwan Kim, "3-D Solenoid Inductor Analysis in a 0.13 μm Digital CMOS Technology," International Journal of Electronics and Electrical Engineering, Vol. 2, No. 4, pp. 286-290, December 2014. doi: 10.12720/ijeee.2.4.286-290
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