Abstract—This paper presented its own design of 12-bit pipeline ADC which has an operating frequency of 8 MHz and consists of 4 stages only. This design is a pipelined ADC with four 3-bit stages (each stage resolves two bits).By doing so, the chip area can be decreased along with minimized power dissipation. In the study’s design, VIN, is first sampled and held steady by a sample-and-hold (S&H), while the flash ADC in stage one quantizes it to three bits. The 3-bit output is then fed to a 3-bit DAC (accurate to about 12 bits), and the analog output is subtracted from the input. This "residue" is then gained up by a factor of four and fed to the next stage. This gained-up residue continues through the pipeline, providing three bits per stage until it reaches the 4-bit flash ADC, which resolves the last 4LSB bits. Because the bits from each stage are determined at different points in time, all the bits corresponding to the same sample are time-aligned with shift registers.

Index Terms—pipeline ADC, time alignment, shift registers, multiplying DAC, flash ADCs, full adder, half adder, delay

Cite: Olga Joy L. Gerasta, Lavern S. Bete, Jayson C. Loreto, Sheerah Dale M. Orlasan, and Honey Mae N. Tagalogon, "12-Bit Pipeline ADC Implemented in 0.09-um Digital CMOS Technology for Powerline Alliance," International Journal of Electronics and Electrical Engineering, Vol. 2, No. 4, pp. 291-297, December 2014. doi: 10.12720/ijeee.2.4.291-297