Abstract—Designing of Phase Locked Loop (PLL) by Design of Experiments (DOE) using Response Surface Methodology (RSM) is presented. Dependence of various design parameters on the three performance characteristics of interest that are Root-Mean-Square-Jitter (RMS-Jitter), Reference Spur level, and Lock time was investigated. Second-order models for RMS-Jitter and Reference Spur level in addition to a first-order with interaction model for Lock time were fitted. Optimization was done to minimize all the three output responses simultaneously using desirability function method and the optimized design was justified experimentally. Experiments were done by simulation using ADIsimPLL provided from Analog Devices.

 

Index Terms—design of experiments, response surface methodology, RMS-jitter, spurs, lock time

Cite: Ibrahim Zohbi and Mohieldin Wainakh, "Designing Phase Locked Loop by Design of Experiments," International Journal of Electronics and Electrical Engineering, Vol. 3, No. 3, pp. 187-190, June 2015. doi: 10.12720/ijeee.3.3.187-190