1. How to submit my research paper? What’s the process of publication of my paper?
The journal receives submitted manuscripts via email only. Please submit your research paper in .doc or .pdf format to the submission email: ijeee@ejournal.net.
2. Can I submit an abstract?
The journal publishes full research papers. So only full paper submission should be considered for possible publication...[Read More]

Design Partitioning Methodology for Systems on Programmable Chip

Abdo Azibi and Ramzi Ayadi
Department of Electronics College of Technology at Alkharj, Saudi Arabia
Abstract—In reconfigurable computing systems, are evolving rapidly, due to their flexibility and high performance. In this paper, we focus on communication cost between partitions in order to develop an algorithm to solve temporal partitioning problems for reconfigurable architecture. In fact, this algorithm optimizes the transfer of data required between design partitions. The proposed algorithm was tested on several examples on the Xilinx Virtex-II pro. The results show significant reduction in the communication cost compared with others famous approaches used in this field.
 
Index Terms—temporal partitioning, data flow graph, system on programmable chip, FPGA

Cite: Abdo Azibi and Ramzi Ayadi, "Design Partitioning Methodology for Systems on Programmable Chip," International Journal of Electronics and Electrical Engineering, Vol. 3, No. 3, pp. 234-239, June 2015. doi: 10.12720/ijeee.3.3.234-239
Copyright © 2012-2021 International Journal of Electronics and Electrical Engineering, All Rights Reserved