Abstract—Different drain-side layout patterns for the 0.25μm 60-V high voltage p-channel Lateral-Diffused MOS device (pLDMOS) devices are investigated in this paper. For the anti-ESD capability evaluation, a drain-side “pnp” arranged-type for a pLDMOS-embedded-SCR structure is used to study this layout type's effect. Here, the layout types of P⁺ region will be treated as some Continuous-Extended (CE) type into the drain-side manners and some Discrete-Distributed (DD) areas into the drain-side architectures, respectively. After all, from Transmission-Line Pulse (TLP) experimental data, it can be found that the DD-type layout manners in the drain-side have a better anti-ESD capability than that of the CE-type, and the secondary breakdown current (I_t2) values can be achieved above 7A (so good their are). On the other hand, the holding voltage (V_h) for the latch-up consideration of the CE-type shows an escalating trend, so it will be with higher anti-electrical-over-stress (EOS) capability. 
 

Index Terms—Electrical-Over-Stress (EOS), Electrostatic Discharge (ESD), embedded-SCR, holding voltage (V_h), p-channel-lateral-diffused MOS (pLDMOS), secondary breakdown current (I_t2), Transmission-Line Pulse (TLP), trigger voltage (V_t1)

Cite: Shen-Li Chen and Yu-Ting Huang, "Design of Reliability Improvement in HV p-Channel LDMOS DUTs by a 0.25μm 60-V BCD Process," International Journal of Electronics and Electrical Engineering, Vol. 4, No. 3, pp. 210-214, June 2016. doi: 10.18178/ijeee.4.3.210-214