Abstract—Content Addressable Memory (CAM) is a storage element similar to Random Access Memory (RAM) used in digital circuits, through which search operations can be done in an extremely high speed. However, usage of CAMs in electronic circuits has been limited because of the high complexity and the high resource usage of CAMs. This paper proposes an efficient design for CAM implementation using traditional RAM. In the proposed method, a primitive CAM block is defined and CAM for the required data width and the address width is created by combining multiples of these CAM primitives. In this research, it has been found that resource usage can be minimized by reducing the data width of this CAM primitive. Investigations were done on how to implement variable sized CAM primitives using fixed sized RAM. It was found that the CAMs implemented using CAM sub-blocks with lower data widths consumes significantly less memory while having a higher latency. This paper shows that the user of the CAM can have a trade-off between resource usage and latency by varying the data width of the primitive CAM which would result in a more optimized and efficient CAM structure.
 

Index Terms—CAM, RAM, memory, FPGA

Cite: Charith P. Wedage, "Efficient Content Addressable Memory Design Using RAM," International Journal of Electronics and Electrical Engineering, Vol. 4, No. 5, pp. 459-462, October 2016. doi: 10.18178/ijeee.4.5.459-462