A 0.6V, 1.3mW CMOS LNA Using Linearity Enhancement Technique
Ehsan Kargaran 1, Mohsen Jamshidi 2,
Abbas Z. Kouzani 3, and
Khalil Mafinezhad 1
1. Microelectronic Laboratory, Sadjad University of Technology, Mashhad, Iran
2. Department of Electrical Engineering, Amirkabir University of Technology, Iran
3. School of Engineering, Deakin University, Geelong, Victoria 3216, Australia
2. Department of Electrical Engineering, Amirkabir University of Technology, Iran
3. School of Engineering, Deakin University, Geelong, Victoria 3216, Australia
Abstract—A highly linear, low voltage, low power, Low Noise Amplifier (LNA) using a novel nonlinearity cancellation technique is presented in this paper. Parallel Inductor (PI) matching is used to increase LNA gain by 3dB at the desired frequency. The linear LNA was designed and simulated in a TSMC 0.18μm CMOS process at 5GHz frequency. By employing the proposed technique, the IIP3 is improved by 12dB in contrast to the conventional folded cascode LNA, reaching -1dBm without having any significant effect on the other LNA parameters such as gain, NF and also power consumption. The proposed LNA also delivers a voltage gain (S21) of 12.25dB with a noise figure of 3.5dB, while consuming only 1.28mW of DC power with a low supply voltage of 0.6V.
Index Terms—first Low Noise Amplifier (LNA), folded cascade, high linear, low power, low voltage, current reuse
Cite: Ehsan Kargaran, Mohsen Jamshidi, Abbas Z. Kouzani, and Khalil Mafinezhad, "A 0.6V, 1.3mW CMOS LNA Using Linearity Enhancement Technique," International Journal of Electronics and Electrical Engineering, Vol. 4, No. 6, pp. 488-493, December 2016. doi: 10.18178/ijeee.4.6.488-493
Cite: Ehsan Kargaran, Mohsen Jamshidi, Abbas Z. Kouzani, and Khalil Mafinezhad, "A 0.6V, 1.3mW CMOS LNA Using Linearity Enhancement Technique," International Journal of Electronics and Electrical Engineering, Vol. 4, No. 6, pp. 488-493, December 2016. doi: 10.18178/ijeee.4.6.488-493
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