Abstract—We introduce SMaRT, a 16-bit single-cycle RISC-type processor with 16-bit-wide instructions. SMaRT features the novel concept of 2.5-address instructions to avoid the data loss that inherently exists in 2-address processors. Additionally, SMaRT’s short-branch instructions take advantage of the temporal locality of reference in accessing the upper or lower halves of the CPU’s 16x16 orthogonal register file. This allows SMaRT to significantly extend the range of the short-branch instructions. We show that these novelties are achieved at almost no performance cost and negligible hardware cost. SMaRT has four operation modes, namely Single-Step, to execute one instruction at a time, Manual, to display and inspect individual locations of data memory, Run, to run the whole code nonstop, and Init, to copy a read-only memory to the data memory for initialization purposes. We also implement and present an input/output port and a sorting coprocessor, and then hook it up to SMaRT through the port as an example. We have successfully synthesized the combined SMaRT and the sorting coprocessor into the Altera Cyclone II FPGA chip, and tested them.
 

Index Terms—2.5-address processors, FPGA synthesis, microcontrollers, microprocessors, RISC, single-cycle CPUs, temporal locality

Cite: Nozar Tabrizi, "SMaRT: Small Machine for Research and Teaching," International Journal of Electronics and Electrical Engineering, Vol. 5, No. 1, pp. 51-58, February 2017. doi: 10.18178/ijeee.5.1.51-58