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A Novel Charge-Protection Superjunction-Insulator VDMOS

Alok Naugarhiya
Department of Electronics and Telecommunication Engineering, National Institute of Technology Raipur, Raipur, C.G. 492010, India
Abstract—A novel charge-protection Superjunction-Insulator (SJ-I) vertical double diffused MOSFET (SJ-VDMOSs) has been proposed. The proposed analytical-model of SJ-I drift layer is verified with the numerical simulation and compared with conventional SJ drift layer model. In the proposed device, we have inserted very thin (100nm) insulator pillar between two consecutive SJ pillars for charge protection and prohibit impurity inter diffusion. This method is optimized Charge Termination (CT) and covers less device area than conventional CT method. In proposed SJ-I devices, the Breakdown Voltage (BV) has been improved by more than 10% with identical area specific ON-resistance (RonA) as compared to conventional SJ devices. Further, we have investigated transfer, output, maximum switching frequency and transient response of SJ-I device.
 
Index Terms—superjunction, breakdown voltage, area specific ON-resistance, charge protection, charge termination

Cite: Alok Naugarhiya, "A Novel Charge-Protection Superjunction-Insulator VDMOS," International Journal of Electronics and Electrical Engineering, Vol. 5, No. 3, pp. 218-222, June 2017. doi: 10.18178/ijeee.5.3.218-222
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