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Memory Efficient LUT Based Address Generator for OFDM-WiMAX De-Interleaver

Bijoy Kumar Upadhyaya 1, Pranab Kumar Goswami 1, and Salil Kumar Sanyal 2
1. Department of Electronics & Telecommunication, Tripura Institute of Technology, Narsingarh, Tripura, India
2. Department of Electronics & Telecommunication, Jadavpur University, Kolkata, India
Abstract—In this paper, a memory efficient Look-up Table (LUT) based address generator for the de-interleaver used in OFDM-WiMAXtransreceiver is proposed. The relationships between various address LUTs implementing different interleaver / de-interleaver depths within a modulation scheme have been exploited to model the proposed address generator. The proposed design shows 81.25% saving of memory blocks in comparison with conventional technique. Hardware structure of the address generator is developed and is converted into a VHDL model using Xilinx Integrated Software Environment (ISE). Simulation results obtained using ModelSim XE-III verifies the functionality of the proposed design. Comparative study of FPGA implementation results of the design on two different platforms is presented. Performance improvement of approximately 30% in terms of maximum operating frequency over a recent work is also obtained.

Index Terms—address generator, de-interleaver, FPGA, LUT, OFDM, VHDL, WiMAX

Cite: Bijoy Kumar Upadhyaya, Pranab Kumar Goswami, and Salil Kumar Sanyal, "Memory Efficient LUT Based Address Generator for OFDM-WiMAX De-Interleaver," International Journal of Electronics and Electrical Engineering, Vol. 2, No. 1, pp. 31-35, March 2014. doi: 10.12720/ijeee.2.1.31-35
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