Abstract—This paper discusses the design of an Integrated Circuit (IC) layout for a decoder. The layout was designed by using an open source software namely Electric VLSI Design System as the Electronic Design Automation (EDA) tool. In order to produce the layout, the basic knowledge of fabrication process and IC design rules are expounded. The complete layout of the decoder was designed based on its schematic circuit, which consists of NOT gates, 2-input NAND gates, 3-input NAND gates, 4-input NAND gates, 2-input AND gates and 3-input AND gates. The layout had undergone Design Rule Check (DRC) set by the Electric VLSI Design System to check for any design rule error. Both layout and schematic circuit of the decoder were then simulated through Layout versus Schematic (LVS) to ensure they were identical. LTspice is used as simulator to carry out the simulation work and verify the validity of the function. The simulation output indicated that results of the layout and schematic circuit for decoder were essentially identical and matches the theoretical results.

Index Terms—decoder, schematic circuit, IC layout, electric VLSI Design System, NAND gates, AND gates and simulation output

Cite: Soh Hong Teen, Li Li Lim, and Jia Hui Lim, "IC Layout Design of Decoder Using Electric VLSI Design System," International Journal of Electronics and Electrical Engineering, Vol. 3, No. 1, pp. 54-60, February 2015. doi: 10.12720/ijeee.3.1.54-60