Abstract—A novel two-split capacitor (T-SC) array structure for Successive Approximation Register (SAR) analog-to-digital converter (ADC) is proposed. When used as digital –to-analog converter (DAC), this circuit reduced the chip area by 27.7% in comparing with the conventional Split Capacitor (SC) at resolution=14. The area reduction effect can be more significant with the increasing resolution of ADC. The capacitor mismatch and parasitic effects of this proposed structure are analyzed in theory. Behavioral simulations were performed to demonstrate the effectiveness of this proposed structure. This simulation was only performed for capacitor mismatch. Simulation results show that T-SC array could achieve good binary-weighted performance and the standard deviation of its DNL was 0.51LSB when the standard deviation of capacitor was 0.025%. Furthermore, the analysis in this paper is provided for designers to make a tradeoff among resolution, CMOS process, circuit structure and capacitor size in their design of SAR ADC.

Index Terms—capacitor DAC, capacitor mismatch, nonlinearity, SAR ADC, small area

Cite: Yingxin Zheng, Zongmin Wang, Song Yang, Qizhang Li, and Li Xiang, "A Novel Two-Split Capacitor Array with Linearity Analysis for High-Resolution SAR ADCs," International Journal of Electronics and Electrical Engineering, Vol. 3, No. 3, pp. 177-181, June 2015. doi: 10.12720/ijeee.3.3.177-181