Abstract—Multi-hit Time-to-Digital Converter (TDC) is an important functional unit in high energy physics (HEP) experiments to measure the accurate arrival time of multiple events. In this paper, a design and implementation of 4-channel Multi-hit TDC using Current Balanced Logic delay (CBL) element in 0.35μm CMOS technology is presented. The merit of CBL logic for tapped delay line provides lowest delay attainable for the delay element allowing better resolution in a given technology node compared to current starved inverter. The TDC is based on time stamping technique, where precise reference timing signals are generated from CBL based Tapped Delay Line (TDL). The TDC is operated in common stop mode, where timing of multiple consecutive hits are measured with respect to trigger. Each channel can measure the timing of four hits. The designed bin size is 150ps and dynamic range can be selected from 10μs to 40μs in steps of 10μs.
 

Index Terms—time-to-digital converter, delay lock loop, current balanced logic

Cite: Pooja Saxena, K. Hari Prasad, and V. B. Chandratre, "Design of Multi-Hit Time-to-Digital Converter Using Current Balanced Logic Delay Element," International Journal of Electronics and Electrical Engineering, Vol. 5, No. 2, pp. 121-126, April 2017. doi: 10.18178/ijeee.5.2.121-126