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A 12-bit 2.88mW 50MHz SAR ADC in 0.18μm CMOS

Chenxi Han 1, Dongmei Li 1, and Dongmei Li 2
1. Electronic Engineering Department of Tsinghua University, Beijing 100084, China
2. Institution of Microelectronics of Tsinghua University, Beijing 100084, China
Abstract—In this paper a 12-bit 2.88mW 50MHz SAR ADC implemented in 180nm CMOS process is presented. A differential split CDAC is adopted which eliminates mismatch of the capacitors. A high-speed and high-resolution dynamic latch comparator is designed to save power. The key path of SA logic module is optimized, achieving 5 basic logic gates and only one DFF delay. The post-layout simulation achieves a SNDR of 60dB with a FOM of 56fJ/conv-step. The core occupies 0.4mm*0.6mm. 
 
Index Terms—analog-to-digital convertor, successive-approximation ADC, differential split charged-DAC, low power

Cite: Chenxi Han, Dongmei Li, and Chenxi Han and Dongmei Li, "A 12-bit 2.88mW 50MHz SAR ADC in 0.18μm CMOS," International Journal of Electronics and Electrical Engineering, Vol. 5, No. 2, pp. 148-151, April 2017. doi: 10.18178/ijeee.5.2.148-151
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