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Implementation of Output Capacitorless LDO Regulator Based on Flipped Voltage Follower for Low Power Applications

Min-Chin Lee, Chong-Lin Shu, and Xiao-Xuan Yang
Department of Electronic Engineering, Oriental Institute of Technology, New Taipei City, Taiwan
Abstract—This paper proposes a based flipped voltage follower Output Capacitorless Low-Dropout (OCL-LDO) regulator with voltage spike detection circuit for low power applications. The OCL-LDO regulator introducing a capacitive coupling circuit at the output of the LDO for output voltage spike detection. The detection circuit uses the transient voltage at the output of the LDO to instantaneously increase the charge and discharge current of the improved Flipped Voltage Follower (FVF). The power transistor gate switching rate can be improved to increase the transient response of the LDO. This based flipped voltage follower OCL-LDO regulator with voltage spike detection circuit is designed using TSMC 0.35μm 2P4M CMOS process technology. According to the simulation and measured results, the circuit with chip area is 1.35×1.35mm2, total chip power dissipation about 0.92mW. Under heavy load condition this chip line regulation is 58mV/V and load regulation is 0.38mV/mA. The chip input supply voltage can operate from 1.6V to 3.3V, the load current from 5mA to 100mA and the output voltage can be stabilized at 1.0V

Index Terms—Output Capacitorless Low-Dropout (OCLLDO) regulator, Flipped Voltage Follower (FVF), load regulation, line regulation, Power Supply Rejection Ratio (PSRR)

Cite: Min-Chin Lee, Chong-Lin Shu, and Xiao-Xuan Yang, "Implementation of Output Capacitorless LDO Regulator Based on Flipped Voltage Follower for Low Power Applications," International Journal of Electronics and Electrical Engineering, Vol. 7, No. 2, pp. 21-26, June 2019. doi: 10.18178/ijeee.7.2.21-26
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