Design of a 8-bits Digitally Controlled Oscillator with Low Power Consumption
Qichao Zha, Tiejun Lu, Jianhui Zhang, and Yu Zong
Beijing Microelectronics Tech. Institution (BMIT), Beijing, China
Abstract—In this paper, a low power consumption 8-bits CMOS digitally controlled oscillator (DCO) design is presented. The CMOS DCO design is based on the logic of SR trigger and the capacitors charging time from input current. Simulations of the proposed DCO using XFAB 0.35μm CMOS processes achieve controllable frequency range of 0~8MHz with a wide range of linearity. It operates over a supply voltage range from 1.8V to 3.6V, a temperature range from -45 to 80°C. Spectre simulation demonstrates that when the frequency of output signal is 8MHz the power consumption of the proposed DCO is 31.78μA and 7.3μA at 1MHz.
Index Terms—digitally controlled oscillator, SR trigger, capacitor charging, low power consumption
Cite: Qichao Zha, Tiejun Lu, Jianhui Zhang, and Yu Zong, "Design of a 8-bits Digitally Controlled Oscillator with Low Power Consumption," International Journal of Electronics and Electrical Engineering, Vol. 3, No. 1, pp. 66-70, February 2015. doi: 10.12720/ijeee.3.1.66-70
Index Terms—digitally controlled oscillator, SR trigger, capacitor charging, low power consumption
Cite: Qichao Zha, Tiejun Lu, Jianhui Zhang, and Yu Zong, "Design of a 8-bits Digitally Controlled Oscillator with Low Power Consumption," International Journal of Electronics and Electrical Engineering, Vol. 3, No. 1, pp. 66-70, February 2015. doi: 10.12720/ijeee.3.1.66-70
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