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A Power and Area Efficient 8-Channel Neural Signal Front End for Biomedical Applications

Sami ur Rehman and Awais Mehmood Kamboh
School of Electrical Engineering and Computer Sciences, National University of Sciences and Technology, Islamabad Pakistan.
Abstract—We present a novel architecture of an ultralow-power and low-area neural signal front-end architecture for telemetry powered Brain Machine Interface (BMI) implanted microchip. Power and chip area are considered two of the most critical parameters in designing neural front ends. The proposed architecture shows better performance as compared to existing designs. The architecture consists of a preamplifier as a gain stage, analog multiplexer for serialization of analog signals and a gain-programmable and band-tunable filter. The filter yielded a midband gain of 40dB ranging from 200Hz to 6KHz; its input referred noise was calculated as 5.2µVrms and a power consumption of 6.2µW. The circuit level design is implemented in 0.5µm CMOS technology with 2.8V supply. The paper discusses architectural and circuit level design and presents a comparison of this work with state of the art architectures. 

Index Terms—biomedical, telemetry, neural, filter, implant, LFP, spikes.

Cite: Sami ur Rehman and Awais Mehmood Kamboh, "A Power and Area Efficient 8-Channel Neural Signal Front End for Biomedical Applications," International Journal of Electronics and Electrical Engineering, Vol. 1, No. 1, pp. 26-30, March 2013. doi: 10.12720/ijeee.1.1.26-30  
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